Ming Zhang received the B.S. degree in physics from Peking University, Beijing, China, in 1999 and the M.S. and Ph.D. degrees in electrical engineering from the University of Illinois at Urbana-Champaign (UIUC), Urbana, IL, in 2001 and 2006, respectively.

Dr. Zhang is a Senior Staff Engineer with Intel Corporation, Santa Clara, CA. His current work focuses on System-on-Chip (SoC) architecture and low-power design methodologies. He has extensive research experiences in the areas of Micro-Electro-Mechanical Systems (MEMS), soft error rate (SER), error-tolerant circuit design, VLSI test, and cache design. He has published more than thirty papers and holds twelve issued or pending U.S. patents in the aforementioned areas. He serves on the program committees of several IEEE conferences and symposia. He has received various research, teaching, and recognition awards from UIUC and Intel.

Patents

1. M. Zhang, S. Mitra, T.M. Mak, and V. Zia, “System and scanout circuits with error resilience circuit,” filed by Intel Corporation, U.S. Patent No. 7,278,076, Oct. 2007.
2. S. Mitra, M. Zhang, T.M. Mak, Q. Shi, and K.S. Kim, “System and shadow circuits with output joining circuit,” filed by Intel Corporation, U.S. Patent No. 7,278,074, Oct. 2007.
3. C. Liu, M. Zhang, and D. Bullen, “Parallel, individually addressable probes for nanolithography,” filed by University of Illinois, U.S. Patent No. 6,867,443, March 2005.
4. C. Liu, M. Zhang, and D. Bullen, “Parallel, individually addressable probes for nanolithography,” filed by University of Illinois, U.S. Patent No. 6,642,129, Nov. 2003.
5. T. Jaber, D. Wu, and M. Zhang, “Common test logic for multiple operation modes,” filed by Intel Corporation, 2008.
6. M. Zhang, C. Wilkerson, G. Taylor, R. Aksamit, and J. Tschanz, “System-driven techniques to reduce memory operating voltage,” filed by Intel Corporation, 2007.
7. M. Zhang, B. Gill, and G. Taylor, “Adaptive memory array design method to improve average power,” filed by Intel Corporation, 2007.
8. M. Zhang, G. Taylor, and N. Seifert, “Noise accommodating information storing apparatus,” filed by Intel Corporation, 2007.
9. K.S. Kim, M. Zhang, and A. Kovacs, “Hierarchical test response compaction for a plurality of logic blocks,” filed by Intel Corporation, 2007.
10. S. Mitra, M. Zhang, and K.S. Kim, “System and shadow bistable circuits coupled to output joining circuit,” filed by Intel Corporation, 2005.
11. T.M. Mak, M. Zhang, S. Mitra, and P. Shipley, “System pulse latch and shadow pulse latch coupled to output joining circuit,” filed by Intel Corporation, 2005.
12. M. Zhang and N.R. Shanbhag, “A method for improving reliability of an electronic system by evaluating a soft error rate,” filed by University of Illinois, 2005.

Publications

Book Chapters

1. S. Mitra, M. Zhang, N. Seifert, T.M. Mak and K.S. Kim, “Soft error resilient system design through error correction,” Springer, 2007, invited.

Journal Publications

1. K.S. Kim and M. Zhang, “Hierarchical test compression for SoC,” IEEE Design and Test of Computers, 2008, in press.
2. M. Zhang and N. Shanbhag, “Dual sampling skewed CMOS design for soft-error tolerance,” IEEE Trans. Circuits and Systems II, Dec. 2006.
3. M. Zhang, et al., “Sequential element design with built-in soft error resilience,” IEEE Trans. VLSI, Dec. 2006.
4. M. Zhang and N. Shanbhag, “Soft-error-rate-analysis (SERA) methodology,” IEEE Trans. CAD, Oct. 2006.
5. S.Mitra, N. Seifert,M. Zhang, Q. Shi, and K.S. Kim, “Robust system design with built-in soft error resilience,” IEEE Computer, Feb. 2005.
6. M. Zhang et al., “A MEMS nanoplotter with high-density parallel dip-pen nanolithography probe arrays,” Nanotechnology, Apr. 2002.
7. C. Chen, M. Cai, X. Wang, S. Xu, M. Zhang, X. Ding, and Y. Sun, “Ferromagnetic properties and structures of the Mn-implanted GaAs semiconductor,” Journal of Applied Physics, May 2000.

Rigorously Refereed Conference Publications

1. M. Zhang, “Design-for-reliability: a soft error case study,” Intl. Test Conf., 2007, invited.
2. M. Zhang et al., “Design for resilience to soft errors and variations,” Intl. On-Line Testing Symp., 2007.
3. N. Seifert, V. Zia, B. Gill, M. Zhang, V. Ambrose, “On the scalability of redundancy based SER mitigation schemes,” Intl. Conf. on IC Design and Technology , 2007, invited.
4. S. Mitra, M. Zhang, N. Seifert, T.M. Mak, and K.S. Kim, “Built-in soft error resilience for robust system design,” Intl. Conf. on IC Design and Technology , 2007, invited.
5. M. Agarwal, B.C. Paul, M. Zhang, S. Mitra, “Circuit failure prediction and its application to transistor aging,” IEEE VLSI Test Symp., 2007.
6. S. Mitra, M. Zhang, S. Waqas, N. Seifert, B. Gill, and K.S. Kim, “Combinational logic soft error correction,” Intl. Test Conf., 2006.
7. S. Mitra, M. Zhang, N. Seifert, T.M. Mak, and K.S. Kim, “Soft error resilient system design through error correction,” IFIP Intl. Conf. on Very Large Scale Integration VLSI-SoC, 2006.
8. M. Zhang and N. Shanbhag, “A CMOS design style for logic circuit hardening,” IEEE Intl. Reliability Physics Symp., 2005.
9. S. Mitra, M. Zhang, T.M. Mak, N. Seifert, V. Zia, and K.S. Kim, “Logic soft errors: a major barrier to robust platform design,” Intl. Test Conf., 2005.
10. S. Mitra, T. Karnik, N. Seifert, and M. Zhang, “Logic soft errors in sub-65nm technologies: design and CAD challenges,” Design Automation Conf., 2005.
11. M. Zhang and N. Shanbhag, “An energy-efficient circuit technique for single event transient noise-tolerance,” IEEE Intl. Symp. on Circuits and Systems, 2005.
12. T.M. Mak, S. Mitra, and M. Zhang, “DFT assisted built-in soft error resilience,” IEEE Intl. On-Line Testing Symp., 2005, invited.
13. M. Zhang and N. Shanbhag, “A soft error rate analysis (SERA) methodology,” IEEE/ACM Intl. Conf. on Computer Aided Design, 2004.
14. D. Bullen, M. Zhang, and C. Liu, “Thermal-mechanical optimization of thermally actuated cantilever beam array,” SPIE’s 9th Annual Intl. Symp. on Smart Structures and Materials, 2002.
15. M. Zhang et al., “Passive and active probe arrays for dip-pen nanolithography,” IEEE Conf. on Nanotechnology, 2001.

Refereed Workshop Publications

1. N. Seifert, V. Zia, B. Gill, M. Zhang, V. Ambrose, “Assessing the impact of scaling on the efficacy of spatial redundancy based SER mitigation schemes,” Silicon Errors in Logic - System Effects Workshop, 2007.
2. M. Agarwal, B.C. Paul, M. Zhang, S. Mitra, “Circuit failure prediction and its application to transistor aging,” Silicon Errors in Logic - System Effects Workshop, 2007.
3. M. Zhang, T.M. Mak, and K.S. Kim, “Fault-tolerant design in the era of variation, degradation, and soft errors,” IEEE Microprocessor Test and Verification Workshop, 2006.
4. M. Zhang and N. Shanbhag, “A transient-tolerant high-performance circuit style,” Workshop on System Effects of Logic Soft Errors, 2006.
5. S. Mitra, M. Zhang, S. Waqas, N. Seifert, B. Gill, and K.S. Kim, “Combinatorial logic soft error correction,” Workshop on System Effects of Logic Soft Errors, 2006.
6. M. Zhang and N. Shanbhag, “Design of soft error tolerant logic circuits,” Workshop on System Effects of Logic Soft Errors, 2005.
7. S. Mitra, M. Zhang, N. Seifert, Q. Shi, T.M. Mak, and K.S. Kim, “Built-in soft error resilience structures,” Workshop on System Effects of Logic Soft Errors, 2005.
8. B. Shim, M. Zhang, and N. Shanbhag, “A novel forward-backward predictor based low-power DSP system,” IEEE Workshop on Signal Processing Systems, 2004.